1. Field of the Invention
The present invention generally relates to digital electronics systems and, more particularly, to the provision of high frequency clock pulses to portions of such digital electronic systems which may be synchronized throughout each such digital electronic systems.
2. Description of the Prior Art
The performance and correct operation of complex digital circuits is critically dependent upon the timing of the signals propagated through the numerous signal paths therein. For example, even with a simple logic gate, if the arrival times of the inputs are skewed in time, the correct output will be produced only during the overlap, if any, of the correct logic states of the input signals. For this reason, the operation of digital circuits is periodically reclocked at intervals referred to as a cycle time. This cycle time is usually determined by a system clock which produces clock signals of different phases to allow for signal propagation and settling times to assure that all signals are in the intended logic state when the various digital circuits are permitted to respond thereto. However, since the cycle times must accommodate all propagation delays and other signal distortion and settling times within the system, the clock cycle must often accommodate the largest delay therein. The cycle time thus imposes this delay on the entirety of the system and therefore limits the operational speed of the entire system.
For the same reasons, the key to improving system speed has been to reduce the propagation times of the individual elements of the digital circuit. This has been quite successful over the years, yielding individual element signal propagation times on the order of 0.1-1.0 nanoseconds and a corresponding cycle time on the order of less than 1 and up to 10 nanoseconds. This cycle time corresponds to a clock rates of 100 Megahertz well into the Gigahertz range.
A problem is encountered, however, in the distribution of clock signals since they must be propagated throughout the entire system to maintain system synchronization, as opposed to the mere clocking of circuits on a single chip, module, card or board where clock signals may be regenerated and propagation paths are limited to a very few inches, at most. Further, the longer system clock signal paths are subject to noise and distortion and may include connections which accentuate these effects, such as inductance which may delay and distort the signal propagation therethrough. Also, line termination impedance mismatch becomes more critical at higher frequencies, causing further distortion. An example of such a connection which exhibits substantial inductance while being otherwise exceptionally reliable, especially for such modular packages as the thermal conduction module (TCM), manufactured by the assignee of the present invention, is the Harcon connector.
Noise and signal propagation delay minimization is therefore achieved by designing the system master oscillator to run at the lowest frequency that synchronous distribution permits in view of the desired system speed. In other words, local, high speed clocks must receive a synchronizing signal from a system synchronizing means at at least a minimum frequency or maximum interval depending on the required accuracy of system synchronization. Conversely, for a given accuracy of system synchronization, the minimum frequency of the synchronization signal must be increased with increasing local, high speed clock rate.
As with the above mentioned connector, difficulties generally begin to arise with clock or synchronization signal frequencies equal to or greater than 100 MHz. It should be understood in this regard that variations in the reactive electrical characteristics of a particular structure, such as a particular parasitic capacitance will have greater effect with increasing frequency. Therefore since parasitic electrical effects often cannot be predicted with precision, the behavior of a particular circuit element becomes less predictable with increasing frequency. However, at the present state of the art, it can be assumed that the behavior of electrical device at 100 MHz and below is well-understood, predictable and highly reliable.
Some electronic construction techniques such as dedicated plane pairs, differential lines, pad-on-pad connectors, shielding and the like are somewhat helpful in reducing noise and propagation delays of clock signals but are neither optimum nor space efficient. Often, such techniques are simply not economically feasible in certain products or cannot be used because of mechanical constraints such as weight or size. Further, connections employing these techniques often would require design modifications which are impractical, costly or require different designs of the same type of electronic component, such as with a particular connector, to accommodate each of several different noise and signal delay techniques. Therefore, even using conventional noise protection techniques, unacceptable noise levels and propagation delays can be anticipated at clock rates of 250 MHz or higher.
Attempts at clock signal regeneration, recovery or reconstruction have been somewhat less successful. Most such techniques involve the prediction or measurement of clock signal propagation delay at a particular point of the system and providing a further delay to cause the regenerated clock signal to coincide with the original clock signal or to have a predetermined offset with respect thereto which will allow proper function of the associated part of the system. However, since these delayed clock signals add a delay which is only controllable during design and which is also subject to noise, such arrangements are not particularly stable and may propagate noise as delay and cause erroneous function of the associated logic. Clock recovery from the input signals is only successful to the extent of providing a clock signal which is generally correct as to the digital signals from which they are recovered. However, such recovered clock signals are not synchronized with the system and may cause anomalous system behavior due to noise and the unpredictable propagation delays which may occur in signals occurring in such portions of the system.
Phase locked loops (PLL's) have been known for many years and are the basis for the familiar process of frequency modulated transmission of radio signals. A phase locked loop is basically a technique to control the frequency of a local oscillator in a manner which will follow variations in frequency of another signal. Therefore, tuners using a phase locked loop exhibit the useful property of being able to "lock on" to a signal close to that of the oscillator or a harmonic or sub-harmonic thereof, depending on the structure of the PLL. Therefore, such tuners are somewhat self-tuning and exhibit particularly good noise immunity. In this and many other common applications of PLL's, the PLL's are basically being used to recover a synchronization signal from the communicated data, similar to the clock recovery arrangements discussed above. Therefore, since the oscillator of the PLL is synchronized to the data received, the system is only locally synchronous and does not exhibit a specific phase correlation with the "transmitter" but only the local timing of the input signal.
A phase locked loop, in its simplest form, includes a variable frequency oscillator, typically a voltage controlled oscillator, and a phase detector. The phase detector receives both an input signal and an output signal from the oscillator. Either the input signal or the oscillator output may be frequency divided depending on whether it is desired for the PLL oscillator to operate at a multiple (e.g. harmonic) or sub-multiple (e.g. sub-harmonic) of the input signal. The phase detector compares the phase of the input signal and the oscillator output and generates a signal (e.g. voltage) having an amplitude corresponding to the phase error detected therebetween to control the oscillation frequency of the variable frequency oscillator. The output of the phase detector is typically low pass-filtered to smooth the error signal and thus stabilize the operation of the voltage controlled oscillator.
Because of the many applications of PLL's in communication systems, many developments and refinements of PLL's have been developed and at the present state of the art, extremely good performance and accurate tracking of an input signal is readily available. For example, low-pass filter circuits for the purpose of stabilizing oscillator operation now preferably include damping to optimize the tracking of the input signal by the oscillator and to avoid overshoot and "hunting". Therefore, PLL's can presently provide excellent tracking of an input signal.